1. Field of Invention
The present invention relates to a method for manufacturing a semiconductor capacitor. More particularly, the present invention relates to a method for manufacturing a dynamic random access memory (DRAM) capacitor.
2. Description of Related Art
FIG. 1 is an equivalent circuit diagram of a DRAM cell. A DRAM cell comprises a transfer transistor T and a storage capacitor C. The source terminal of a transfer transistor T is connected to a bit line BL, and the drain terminal is connected to a storage electrode 10 of a storage capacitor C. The gate terminal of the transfer transistor is connected to a word line WL. The opposed electrode 12 is connected to a fixed voltage source. A dielectric layer 14 is formed between the storage electrode 10 and the opposed electrode 12.
FIG. 2 is a cross-sectional view showing the basic structure of a conventional DRAM device. As shown in FIG. 2, the method of fabricating a DRAM cell comprises the step of forming a plurality of field oxide layers 21 on a P-type substrate 20. The field oxide layers 21 not only define the device regions, but also act as a device isolation structure. Thereafter, a gate oxide layer 22, a polysilicon layer 23 and an upper cap oxide layer 24 are sequentially formed over the substrate 20 forming a gate structure as shown in FIG. 2. Subsequently, protective oxide spacers 25 are formed on the sidewalls of the gate structure.
Next, a self-aligned process is used to form source/drain regions 26a and 26b in the substrate 20, thus finishing the fabrication of a MOS transistor. After that, a polysilicon layer having electrical connection with one source/drain region 26b is formed by a conventional method. The polysilicon layer acts as a bit line 27. In a subsequent step, an insulating layer 28, for example, an oxide layer, is formed over the substrate 20 and gate structure. Next, using photolithographic and etching processes, the insulating layer 28 is patterned to form a self-aligned contact window 29 exposing the source/drain region 26a. Finally, a conductive layer is deposited over insulating layer 28 and into the contact window 29, and then patterned to form the lower electrode of the capacitor.
Due to the restriction imposed by the resolution of light source in a photolithographic process, there is a minimum size for the contact window 29. If attempt is made to narrow down the contact window 29 and surrounding structures without due regard to possible errors caused by the ultimate resolution, the insulating material for isolating the gate 23 from subsequently deposited conductive layer may be too thin and may result in short-circuiting. Thus, reliability of the device is compromised.
In the meantime, the charge storage capacity of a capacitor needs to be increased. Therefore, new dielectric materials that has a higher dielectric constant or new methods that are capable of depositing a thinner and better quality dielectric layer are constantly in need. Yet, how to increase the surface area of a charge storage electrode despite the continuous shrinking of available DRAM substrate area remains to be a major issue in semiconductor fabrication.
At present, various methods for increasing the surface area of the capacitor's lower electrode are devised. Most of them make use of fabricating three-dimensional structures and forming uneven surfaces. For example, all kinds of structural shapes for the lower electrode, such as a crown, a pillar, a fin, a tree-trunk with branches or a cavity, exist. In addition, a hemispherical grained silicon (HSG-Si) layer can be formed over the surface of an electrode to increase the charge storage capacity of a capacitor by up to about 80 percent. However, the capacitance of a capacitor can still be increased by following an improved method of manufacturing.